Semiconductor device structure including a tantalum pentoxide layer sandwiched between silicon nitride layers

ABSTRACT

An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiN x ) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta 2 O 5 ) layer. The SiN x  cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer Si x N y /Ta 2 O 5 /Si x N y  structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer. An exemplary shallow trench isolation structure includes the Si x N y /Ta 2 O 5 /Si x N y  structure as a liner on the sides and bottom of a shallow trench in the surface of a substrate. The shallow trench is filled with an oxide, such as TEOS. A variety of methods may be used for fabricating devices that include the Si x N y /Ta 2 O 5 /Si x N y  structure.

This application is a division of application Ser. No. 09/259,001, filed Feb. 26, 1999, now U.S. Pat. No. 6,294,807.

FIELD OF THE INVENTION

The present invention relates to integrated circuit devices and methods for fabricating an integrated circuit and, in particular, monolithic capacitors.

DESCRIPTION OF THE RELATED ART

Research has focussed on finding an insulating film having a high dielectric constant suitable for use in capacitor elements, such as capacitor elements of memory cells in dynamic random access memory (DRAM) devices or other memory devices.

Of the insulating films having high dielectric constants, a tantalum pentoxide (Ta₂O₅) film formed by chemical vapor deposition (CVD) has been intensely studied. This is because the tantalum pentoxide film has a large dielectric constant ranging from 25 to 30 and has excellent step-coverage characteristics compared to other dielectric materials, and is more easily deposited than other materials having a high dielectric constant.

U.S. Pat. Nos. 5,438,012 and 5,352,623 to Kamiyama (hereinafter, “the '012 patent” and “the '623 patent”) and U.S. Pat. No. 5,696,017 to Ueno (hereinafter, “the '017 patent”) are all incorporated by reference herein in their entireties, for their teachings on methods for forming a capacitor element within an integrated circuit, wherein tantalum pentoxide is used as the dielectric material for the capacitor insulator layer.

In the '012 patent, as shown in FIG. 4A a silicon nitride film 24 is formed on a polysilicon electrode 3 by a quick heat treatment using ammonia gas (NH₃). Then, as shown in FIG. 4B, an impurity-doped tantalum pentoxide (Ta₂O₅) film 5 is deposited by the CVD process. Subsequently, as shown in FIG. 4D, a titanium nitride (TiN) film 6 is formed as an upper electrode 6.

In the '623 patent, the surface of a polysilicon film 2 is subjected to rapid thermal nitriding (RTN) by lamp-annealing or lamp heating, through which the polysilicon surface is reacted with nitrogen to form a silicon nitride film (SiN_(x)). Then, a tantalum pentoxide film 11 is formed on the lower capacitor electrode 2 by plasma enhanced chemical vapor deposition. The tantalum pentoxide film 11 is densified by a thermal treatment in an oxidizing atmosphere using an electric furnace, then nitrided by a plasma treatment with ammonia by use of a plasma-ion generator. Then, a titanium nitride layer is formed as the upper capacitor electrode 3 on the tantalum pentoxide film 11.

The '017 patent teaches that in a capacitor having a tantalum pentoxide insulating layer, it is also acceptable to use W, Mo, TiW, Pt, WN, MoN, TiWN, WSi, WSiN etc., instead of TiN as the upper electrode metal.

Tantalum pentoxide, as deposited, has excellent dielectric properties. Experience in prior art devices shows that the Tantalum tends to diffuse into the surrounding layers during subsequent heat treatment, tantalum pentoxide tends to diffuse into the upper or lower layers of the device in which they are used. This may have adverse consequences due to the metal contaminants. Improved structures and methods for integrated circuit capacitors is desired.

SUMMARY OF THE INVENTION

The present invention is an insulating structure that includes: a first silicon nitride layer; a second silicon nitride layer separate from the first silicon nitride layer; and a tantalum pentoxide layer formed between the first and second silicon nitride layers. Other aspects of the present invention include semiconductor devices including the insulating structure, and a method of fabricating the insulating structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a first exemplary device including an insulating structure according to the invention, wherein the device is a metal-oxide-metal (MOM) capacitor.

FIG. 2 illustrates a second exemplary device including an insulating structure according to the invention, wherein the device is a metal-oxide-polysilicon (MOP) capacitor.

FIG. 3 illustrates a third exemplary device including an insulating structure according to the invention, wherein the device is a polysilicon-oxide-silicon (POS) capacitor.

FIG. 4 illustrates a fourth exemplary device including an insulating structure according to the invention, wherein the device is a polysilicon-oxide-polysilicon (POP) capacitor.

FIG. 5 illustrates an exemplary circuit including an insulating structure according to the invention, wherein the insulating structure is part of a shallow trench isolation structure.

DETAILED DESCRIPTION

The present invention is an insulating structure which includes a tantalum pentoxide (Ta₂O₅) layer surrounded on both sides by silicon nitride (SiN) layers, and a method of forming the structure. By cladding the tantalum pentoxide (Ta₂O₅) layer with silicon nitride layers on both sides, the tantalum pentoxide is trapped and diffusion of tantalum is prevented. The high dielectric properties of the tantalum pentoxide are retained.

One of the main problems experienced with conventional oxides is the diffusion of tantalum out of the Ta₂O₅ layer upon subsequent heatings of the device during manufacture. The invention solves this problem by cladding the tantalum pentoxide layer with silicon nitride diffusion barrier layers on both sides, to prevent diffusion of the tantalum without degrading the dielectric properties of the composite structure.

In capacitors, such as polycrystalline silicon-oxide-polycrystalline silicon (hereinafter, polycrystalline silicon is referred to as “polysilicon”) or metal-oxide-metal (MOM) a high dielectric constant k is desired.

With conventional oxides such as SiO, WN, and WSiN, tantalum pentoxide tends to exhibit poor heat stability. Sandwiching the Ta₂O₅ layer between two layers of SiN, according to the invention, substantially eliminates the heat sensitivity problem. Thus, the combined SiN/Ta₂O₅/SiN structure can be used in various applications where heat sensitivity is an important factor.

One of the other benefits of the integrated circuit fabrication method and structure of the present invention is its high dielectric constant (k). Since, SiN has a higher dielectric constant (k=2.9) than conventional oxides such as SiO₂ (k=2.0), the charge storage capability of the capacitor is enhanced.

Further, the invention provides improved thermal stability compared to conventional WN_(x), and WSiN_(x) structures. Metals tend to break down more quickly than silicon nitride. If tantalum pentoxide is encapsulated with WN_(x), WSiN_(x), or TiN structures, and subsequent thermal processing is performed, the properties of the resulting structure would be more temperature sensitive than a Si_(x)N_(y)/Ta₂O₅/SiN structure according to the present invention.

Thus, the overall dielectric constant of an integrated circuit including the SiN/Ta₂O₅/SiN structure is higher than conventional structures. As is well known in the art, a higher dielectric constant provides better capacitance characteristics. In addition, improved thermal stability is provided by the invention.

In the embodiments described below with reference to FIGS. 1-5, reference is frequently made to the silicon nitride composition as SiN, for the sake of brevity only. In each of the embodiments described below, the silicon nitride cladding may be formed of other compositions of silicon and nitrogen having the form Si_(x)N_(y). Thus, the insulating structure according to the invention may more generally be represented as Si_(x)N_(y)/Ta₂O₅/Si_(x)N_(y).

Although the embodiments described below with reference to FIGS. 1-5 all include only a single insulating layer of tantalum pentoxide between the two silicon nitride layers, the insulating layer between the two silicon nitride layers may include additional layers. For example, a bi-layer or tri-layer dielectric structure having at least one tantalum pentoxide layer may be sandwiched between the two silicon nitride layers. Such structures are contemplated within the scope of the present invention.

FIG. 1 shows a first embodiment of the present invention wherein the insulating structure is included in a metal-oxide-metal (MOM) capacitor structure 100. The capacitor 100 has a central insulating portion 130, surrounded on both sides by first and second electrode layers 120 and 140, respectively.

The central insulating portion 130 includes a layer 132 of tantalum pentoxide (Ta₂O₅) sandwiched between silicon nitride (Si_(x)N_(y)) layers 131 and 133. The silicon nitride layers 131 and 133 may each be at least about 50 Angstroms thick. The tantalum pentoxide layer 132 may be at least about 100 Angstroms thick. As explained above, the silicon nitride layers 131 and 133 provide a higher dielectric constant than other dielectrics such as silicon dioxide (SiO₂), tungsten nitride (WN), or tungsten silicon nitride (WSiN), and also provides excellent thermal stability.

The first electrode structure 120 may include metal, such as, for example, a first layer 121 of aluminum (Al) and a second layer 122 of TiN. The first electrode 120 may be formed of other materials, such as W, Mo, TiW, Pt, WN, MoN, TiWN, WSi, WSiN and the like, instead of TiN. Alternatively, a conductive material such as polysilicon may be used.

The second electrode 140 may be a layer of metal, and may include a single layer of titanium nitride (TiN) 141. It is also acceptable to use W, Mo, TiW, Pt, WN, MoN, TiWN, WSi, WSiN and the like, instead of TiN as the upper electrode metal. Alternatively, a conductive material such as polysilicon may be used.

FIG. 2 shows a second embodiment of the present invention wherein the insulating structure is included in a metal-oxide-polysilicon (MOP) capacitor 200. This second embodiment is similar to the capacitor of FIG. 1. The main difference is that in capacitor 200, the first electrode layer 220 includes a layer of TiN 222 sandwiched between a polysilicon layer 221 and the central oxide portion 230.

The first electrode 220 of capacitor 200 includes a polysilicon layer 221 and a TiN layer 222. The insulating structure 230 includes a first silicon nitride layer 231, a tantalum pentoxide layer 222, and a second silicon nitride layer 223. The second electrode 240 may include a layer of TiN. It is also acceptable to use other materials, such as W, Mo, TiW, Pt, WN, MoN, TiWN, WSi, WSiN and the like, or polysilicon, instead of TiN as the material for the first and/or second electrodes 220 and 240.

FIG. 3 shows a third embodiment of the present invention where the insulating structure is included in a polysilicon-oxide-silicon (POS) capacitor 300. Capacitor 300 is similar to the capacitor of FIG. 1, except that the first electrode 320 includes a polysilicon layer 321 having an SiO₂ diffusion barrier layer 322 formed thereon, and the second electrode 340 includes a polysilicon layer 341.

The first electrode 320 of capacitor 300 includes a polysilicon layer 321 and an SiO₂ diffusion barrier layer 322. The insulating structure 330 includes a first silicon nitride layer 331, a tantalum pentoxide layer 322, and a second silicon nitride layer 323. The second electrode 340 may include a layer 441 of polysilicon. It is also acceptable to use other materials, such as W, Mo, TiW, Pt, WN, MoN, TiWN, WSi, WSiN and the like, instead of polysilicon as the material for the first and/or second electrodes 320 and 340.

FIG. 4 shows a fourth embodiment of the present invention where the insulating structure is included in a polysilicon-oxide-polysilicon (POP) capacitor 400. This fourth embodiment is similar to capacitor 300, except that the first electrode layer 420 comprises a layer of TiN 422 sandwiched between a polysilicon layer 421 and the central insulating structure 430.

The first electrode 420 of capacitor 400 includes a polysilicon layer 421 and a TiN layer 422. The insulating structure 430 includes a first silicon nitride layer 431, a tantalum pentoxide layer 422, and a second silicon nitride layer 423. The second electrode 440 may include a layer 441 of polysilicon. It is also acceptable to use other materials, such as W, Mo, TiW, Pt, WN, MoN, TIWN, WSi, WSiN and the like, instead of polysilicon as the material for the first and/or second electrodes 420 and 440.

The exemplary capacitor structures 100, 200, 300, 400 may be formed by modifying conventional fabrication techniques to includes steps for forming the three-layer Si_(x)N_(y)/Ta₂O₅/Si_(x)N_(y). structure. For example, capacitors may be formed by modifying the fabrication methods of the '623 or '017 patents (both incorporated by reference herein) to add a step of forming a second silicon nitride layer over the tantalum pentoxide layer, before forming the upper electrode layer. In these examples, appropriate thickness is used for the two silicon nitride layers (e.g., about 50 Angstroms) and the tantalum pentoxide layer (e.g., about 100 Angstroms).

FIG. 5 shows a fifth embodiment of the present invention wherein an integrated circuit configuration 500 includes a shallow trench isolation structure 501. Shallow trench isolation structures are well known in the art for providing isolation between different devices on an integrated circuit substrate. Formation of shallow trench devices is well known in the art. An exemplary method for forming a shallow trench isolation structure is described in U.S. Pat. No. 5,854,114 to Li et al., (hereinafter, “the '114 patent) which is incorporated by reference herein in its entirety.

The shallow trench isolation structure 501 shown in FIG. 5 includes a liner 502 which is substantially similar to the three-layer SiN/Ta₂O₅/SiN composite structure described above with reference to FIGS. 1-4.

The shallow trench isolation structure 501 may include a silicon substrate 510 and an epitaxial silicon layer 515. Shallow trenches are formed in the surface of epitaxial layer 515, by a conventional process. The SiN/Ta₂O₅/SiN liner 502 is formed on the side and bottom surfaces of the shallow trenches. The lined trenches are then filled with an oxide such as tetraeythylorthosilicate (TEOS) 503. A polysilicon layer 520 is formed over the TEOS 503. The other devices in the configuration 500 may be the same as shown and described in the '114 patent, including a thin tunnel oxide 505 and a programming junction implant 535.

The fabrication method of the exemplary circuit configuration 500 may be similar to that described in the '114 patent, except that the liner oxide layer 120 in the '114 patent is replaced by the SiN/Ta₂O₅/SiN liner structure 502 in FIG. 5 of this application. Thus, all of the fabrication steps of the '114 patent may be followed, except for the step of forming the liner oxide 120.

A shallow trench isolation structure according to the invention has the SiN/Ta₂O₅/SiN liner structure. One of ordinary skill recognizes that shallow trench isolation configurations other than that shown in the '114 patent may be formed with a SiN/Ta₂O₅/SiN liner structure according to the present invention, and the shallow trench isolation structures may be used between any variety of active devices.

Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claim should be construed broadly, to include other variants and embodiments of the invention which may be made by those skilled in the art without departing from the scope and range of equivalents of the invention. 

What is claimed is:
 1. A method of forming a semiconductor device, comprising the steps of: forming a first silicon nitride layer overlying at least a portion of a substrate; forming a tantalum pentoxide layer above the first silicon nitride layer; and forming a second silicon nitride layer above the tantalum pentoxide layer; further comprising the steps of: forming a first electrode overlying at least a portion of the substrate, wherein the first silicon nitride layer is formed above the first electrode; and forming a second electrode above the second silicon nitride layer, thereby to form a capacitor.
 2. The method of claim 1, wherein the first and second silicon nitride layers are at least about 50 Angstroms thick.
 3. The method of claim 1, wherein the tantalum pentoxide layer is at least about 100 Angstroms thick.
 4. The method of claim 1, wherein at least one of the first electrode and the second electrode forming steps includes forming a metal containing layer.
 5. The method of claim 1, wherein at least one of the first electrode and the second electrode forming steps includes forming a titanium nitride layer.
 6. The method of claim 1, wherein at least one of the first electrode and the second electrode forming steps includes forming a layer of titanium nitride and a layer of aluminum.
 7. The method of claim 1, wherein at least one of the group consisting of the first electrode and the second electrode is a polysilicon layer.
 8. The method of claim 1, wherein the first electrode is formed above a polysilicon substrate.
 9. The method of claim 1, further comprising the step of forming a layer of silicon dioxide above a silicon substrate, wherein the first electrode is formed above the layer of silicon dioxide.
 10. A method of forming a semiconductor device, comprising the steps of: forming a first silicon nitride layer overlying at least a portion of a substrate; forming a tantalum pentoxide layer above the first silicon nitride layer; and forming a second silicon nitride layer above the tantalum pentoxide layer further comprising the steps of: providing a substrate having a shallow trench on a surface thereof, the shallow trench having a bottom surface and a side surface, the shallow trench being located between two active devices on the substrate, the first silicon nitride layer being formed over the bottom and side surfaces of the shallow trench; and forming an oxide layer above the second silicon nitride layer, thereby to form a shallow trench isolation structure.
 11. The method of claim 10, wherein the oxide layer contains tetraeythylorthosilicate. 